1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, for example, to the method which is required to provide a gate length smaller than an exposure limit, and to fabricate a gate butt portion.
2. Background Art
In the semiconductor industry, employment of various processing techniques has led to smaller design rules with each passing year. For example, a gate length smaller than an exposure limit can be provided by performing exposure at an exposure limit and then reducing the gate length when a gate etching is performed (hereinafter referred to as “trimming”). Further, use of a Levenson mask enables to form a pattern finer than a conventional pattern, using light having a conventionally used wavelength (see U.S. Pat. No. 5,858,580).
However, the trimming causes problems in forming opposed end portions of gate electrodes of adjacent SRAM cells, which are called “gate butt portions”, as shown in US 2007/0072131 A1. In fact, the distance between the gate butt portions becomes larger due to the trimming. Therefore, it is impossible to concurrently realize both of providing a gate length smaller than an exposure limit and fabricating the gate butt portions by one exposure. Therefore, “double exposure”, in which a gate etching is performed by two exposures, is receiving increasing attention (see U.S. Pat. No. 6,042,998).
However, the double exposure raises such problems as an increase of a manufacturing cost of LSIs due to an increase of the number of steps, an increase of the number of times of post-processing, and a difficulty in applying BARC (Bottom Anti-Reflection Coating) for the second exposure. The BARC is an anti-reflection coating formed as a sublayer of a resist. Therefore, in the case where the double exposure is employed, it is desired that these problems or a problem caused by these problems should be suppressed.